1. Field of the Invention
The present invention relates to a design method for a semiconductor integrated circuit, specifically to a design method for LSI in which an uncertain amount of timing is adjusted while eliminating factors relative to determined timings during a design process thereof.
2. Description of the Related Art
In recent years, the design of a semiconductor integrated circuit is required for consideration of influences by an on-chip variation and a cross-talk, besides LSI for use in high speed operations, a convergence of timing has been increasingly difficult. This makes it important to establish an uncertain amount of timing (“timing uncertainty” hereinafter) as a timing margin. In the conventional common design method, however, a fixed timing margin has been established in the logic synthesis stage, followed by the design accordingly.
FIG. 1 shows a flow chart of such a conventional LSI design method. In FIG. 1, first a timing margin as common condition which does not depend on a product specification is established, as a margin responding to an operating frequency for example, and a logic synthesis is performed by using a library content which is stored characteristics of the cells, followed by repeating the above described steps until a layout design and a verification of the result are complete. When the result of the verification becomes OK, a sign-off is achieved and thus the product is transferred from the design process to a subsequent process.
In such a conventional LSI design process, a fixed timing margin has been established for all product specification in the logic synthesis stage and the design has been carried out accordingly. Since relationships among clock tree structure, layout process and sign-off condition have not been taken into consideration in establishing the timing margin, the last sign-off verification has been faced with a timing convergence problem, resulting in a numerous repetition of the layout design and the verification. Besides, since the conventional establishing method for timing margin has not taken a condition of a product specification into consideration, thus precluding a timing margin optimization in accordance with an applicable product specification or a reestablishment of margin even if each process is faced with a problem in timing convergence. Such has been the problem.
Such a conventional technique relating to a design method for a semiconductor integrated circuit is seen in the following document.
[Patent document 1] Japanese patent laid-open application publication 2001-196459 (P2001-196459A): “Design method and apparatus for a semiconductor integrated circuit”
This document has disclosed a design method for a semiconductor integrated circuit comprising a first step for temporarily defining a logic circuit having a required specification, a second step for calculating a timing margin in accordance with an operating frequency of the logic circuit and a third step for modifying a design parameter of the logic circuit temporarily defined in accordance with the calculated timing margin, and enabling a quick and appropriate design of a required semiconductor integrated circuit.
The technique disclosed in the document above, however, the timing margin is defined only in accordance with the operating frequency, therefore the method has been faced with a problem of precluding an adoption of this method if the customer requirement of operating frequency cannot be changed and an applicability of such timing margin common to all the design processes.